1. Field of the Invention
The present invention relates to a semiconductor test apparatus and method thereof and a multiplexer and method thereof, and more particularly, to a semiconductor test apparatus for detecting memory failure and method thereof and a multiplexer with a reduced size and method thereof.
2. Description of the Related Art
A Built-In-Self-Test (BIST) circuit may be a self-testing circuit, and may be embedded in a semiconductor device for testing the semiconductor device. The BIST circuit may write test data to the semiconductor device to test the semiconductor device, and may then compare an expected value with an output value read from the semiconductor device. This comparison may determine whether memory failure occurs in the semiconductor device. In other words, the BIST circuit may write the test data to the semiconductor device, and may then determine whether memory failure occurs in the semiconductor device by determining whether a desired output value is received from the semiconductor device. A conventional BIST circuit may test a semiconductor memory device.
A conventional BIST circuit for testing a semiconductor memory device may write a test data to the semiconductor memory device. The semiconductor memory device may have a memory failure in at least one of a plurality of cells within the semiconductor memory device and/or in a control circuit for controlling the semiconductor memory device. Various conventional tests may be used for testing the semiconductor memory device. These conventional tests may include a march pattern test, a checkerboard pattern test, and/or a retention test. These conventional tests are well-known in the art and will not be described further for the sake of brevity.
FIG. 1 illustrates a block diagram of a prior art semiconductor test apparatus.
Referring to FIG. 1, the semiconductor test apparatus may include an embedded memory 60, a BIST controller 30 and multiplexers 10 and 20. The BIST controller 30 may output test signals for determining whether a failure exists in the embedded memory 60. The multiplexers 10 and 20 may connect the embedded memory 60 with the BIST controller 30.
The BIST controller 30 may generate a test data Bist_D, may write the test data Bist_D to the embedded memory 60, may read the data DOUT, the data DOUT corresponding to the test data Bist_D from the embedded memory 60, and may compare the read data DOUT with a desired value to determine whether a failure exists in the embedded memory 60.
The multiplexers 10 and 20 may supply the embedded memory 60 with the test data Bist_D and a control signal Bist. Alternately, the multiplexers 10 and 20 may supply the embedded memory 60 with the data Normal_D and a control signal Normal. The multiplexers 10 and 20 may select the test data Bist_D and the control signal Bist during a test mode, and may select the data Normal_D and the control signal Normal a normal mode, the mode being determined by a mode signal.
When not in a test mode, the multiplexers 10 and 20 may select the data Normal_D and the control signal Normal, and the data Normal_D may be written to an address of the embedded memory 60. The address may be determined by the control signal Normal.
When in a test mode, the multiplexers 10 and 20 may select the test data Bist_D and the control signal Bist, and the test data Bist_D may be written to an address of the embedded memory 60. The address may be determined by the control signal Bist.
However, since each signal input to the embedded memory 60 goes through the multiplexers 10 and 20, the area occupied by the multiplexers 10 and 20 may scale with a number of signal inputs. As the area allotted to the multiplexers 10 and 20 increases, greater consideration may be necessary when designing a semiconductor device including the multiplexers 10 and 20.
When designing a conventional semiconductor device, a designer may consider fault coverage. Herein, fault coverage means a ratio of a number of detected faults (i.e. memory failures) to a total number of faults. For example, a detected fault with respect to a semiconductor memory device may be an addressable portion of the semiconductor memory device determined to have a memory failure. In another example, the fault coverage for a first semiconductor memory device may be determined to be 95%. This may indicate that 95% of the total number of faults in the semiconductor memory device are detectable. Recovery operations in response to a detected fault may be initiated only if an address of the fault is known.
Conventional semiconductor devices may have a plurality of input pins and a plurality of output pins. Test data may be input through the plurality of input pins. The inputted test data may be processed in the semiconductor device and the result may be output through the plurality of output pins. In the example of a semiconductor memory device, the processing may include writing the test data to a first portion of memory, reading the first portion of memory, and outputting the data read from the first portion of memory.
In order to detect a fault, a semiconductor device may receive test data through at least one of the plurality of input pins. A result based on the received test data may be output on at least one of a plurality of output pins. An analysis of the result may indicate whether a memory fault has occurred.
Conventional fault detection may be applied in a combinational logic circuit (CLC). However, fault detection may be more difficult to achieve in a sequential logic circuit (SLC) because an output from the SLC may lag an input to the SLC by at least one clock cycle. An example of a SLC may be a flip flop. Accordingly, it may be difficult to achieve accurate fault detection in semiconductor devices that include a plurality of flip flops.
Conventional fault detection applied to a semiconductor device including a plurality of flip flops may include configuring the plurality of flip flops to function as scan cells and chaining the plurality of flip flops together. Thus, a plurality of flip flops (i.e. SLCs) configured as scan cells and chained may function similar to a CLC.
FIG. 2 illustrates a conventional scan cell circuit 50. Referring to FIG. 2, the scan cell circuit 50 may include a multiplexer 51 and a flip flop 52. The multiplexer 51 may output one of a data input DI and a scan input SI based on a select signal SE. The flip flop 52 may output of the selected output of the multiplexer 51 as a final output SO in response to a clock signal CK.
The scan cell circuit 50 may include a capture mode and a shift mode, the mode being determined by a select signal SE.
In the capture mode, when the select signal SE is ‘0’, data input DI may be selected by the multiplexer 51. The selected data input DI may be applied to a data input terminal D of the flip flop 52 so that the scan cell circuit 50 may operate as a flip flop with a delay due to a propagation time within the multiplexer 51.
In the shift mode, when the select signal SE is ‘1’, scan input SI may be selected by the multiplexer 51. The selected scan input SI may be applied to the data input terminal D of the flip flop 52, so that the desired data for fault detection may be applied to the data input terminal D as the scan input SI.
Conventional semiconductor devices may include an embedded memory. Examples of embedded memory may include read only memory (ROM) and random access memory (RAM). If a scan cell circuit is connected to an embedded memory, data received by the embedded memory from the scan cell circuit may be shifted so that no problem occurs. However, in the capture mode, output may be delayed by at least one cycle due to the flip flop of the scan cell circuit. Thus, since the embedded memory may employ a scan cell circuit in place of a flipflop, it may not be possible to detect a fault with conventional fault detection.
In the conventional semiconductor device including an embedded memory, automatic test pattern generation (ATPG) may not be performed on the embedded memory. Since ATPG may not be used, a BIST circuit may be used on the embedded memory to determine whether memory failure exists. When ATPG is performed, the embedded memory may be processed with the input/output (I/O) terminals of the embedded memory being excluded. Thus, it may not be possible to detect faults of all the I/O terminals. Since it may not be possible to detect faults in the semiconductor device including the embedded memory, the fault coverage of the semiconductor device including the embedded memory may decrease. Accordingly, in order to detect faults of the embedded memory, scan cell circuits may be employed in order to increase the fault coverage of the conventional semiconductor device including the embedded memory.
FIG. 3 illustrates a block diagram of a conventional semiconductor test apparatus 380. The semiconductor test apparatus 380 may include logic circuits 305, 310 and 315, embedded memory 60 and scan cell circuits 40 and 50. The scan cell circuit 50 of FIG. 3 may function similar to the scan cell circuit 50 of FIG. 2.
Referring to FIG. 3, the semiconductor test apparatus 380 may include an address and control signal AC a data input DI and a data output D01. The address and control signal AC, data input DI and data output D01 may represent a plurality of address and control signals, data inputs, and data outputs, respectively.
Referring to FIG. 3, the scan cell circuit 40 may include a multiplexer 41 and a flip flop 42. The multiplexer 41 may select one of the address and control signal AC and a scan input SI based on a scan signal SE. The flip flop 42 may output the selected output of the multiplexer 41 in response to a clock signal CK.
The scan cell circuit 50 may function similar to the scan cell circuit 50 as described with respect to FIG. 2. A tri-state buffer 70 may receive the output of the scan cell circuit 50. The tri-state buffer 70 may select between a normal mode and a test mode based on a test enable signal TE.
Operation of the tri-state buffer 70 will now be described. In the normal mode, the test enable signal TE may be applied as ‘0’ and data may be inputted and/or outputted to and from the embedded memory 60. In the test mode, the test enable signal TE may be applied as ‘1’.
When the test enable signal TE is ‘1’, indicating a test mode, and the scan signal SE is ‘1’, indicating a shift mode, the multiplexer 51 may select the scan input SI as output to the flip flop 52. The selected scan input SI may be received by the tri-state buffer 70 from the flip flop 52 in response to a clock signal CK. Alternatively, when the test enable signal TE is ‘1’, indicating a test mode, and the scan select SE is ‘0’, indicating a capture mode, the multiplexer 51 may select the data input DI as output to the flip flop 52. The selected data input DI may be received by the tri-state buffer 70 from the flip flop 52 in response to the clock signal CK.
If the scan cell circuits 40 and 50 are chained, the desired data may be applied as the scan input at the ATPG and is shifted to a desired node so that a fault is detected. In this case, the input node AC or DI inputted to the embedded memory 60 may be controlled at input pins of the semiconductor test apparatus 380. In addition, the output node DOUT may be read at the output of the semiconductor test apparatus 380 with a shift operation.
Thus, the signals of the embedded memory 60 may be observed. Accordingly, fault coverage for the semiconductor test apparatus 380 may be increased.
However, if the number of scan cell circuits included to improve fault coverage of the embedded memory 60 increases, the size (i.e. area) of the semiconductor test apparatus 380 may be increased. Furthermore, since the semiconductor test apparatus 380 may be a portion of a large scale integrated circuit, including a plurality of embedded memories 60, the increase to the size of the semiconductor test apparatus 380 may scale with the number of embedded memories 60, as each of the plurality of embedded memories 60 may include a plurality of scan cell circuits.